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Intel MIC Programming Workshop @ LRZ

Po, 27.06.2016 9:00 - St, 29.06.2016 18:00
Leibniz Supercomputing Centre (LRZ), Garching u Mnichova, Německo

Vybíráme z oficiální pozvánky na Intel MIC Programming Workshop na LRZ :

We are pleased to announce that LRZ will offer a 3-day PRACE Advanced Training Centre (PATC) workshop on June 27-29, 2016 completely devoted to Intel Xeon Phi programming. The course discusses Intel's Many Integrated Core (MIC) architecture in detail and covers various programming and optimisation techniques for Intel Xeon Phi coprocessors.

The first two days provide an introduction about the Intel MIC architecture and various Intel Xeon Phi programming models, interleaved with many hands-on sessions on the Intel Xeon Phi based SuperMIC system at LRZ.

The last day presents advanced topics about performance optimisation and Intel's new Knights Landing (KNL) architecture.

During a plenum session invited speakers from Intel, RRZE, IPP, IT4Innovations, IPCC @ TUM and IPCC @ LRZ talk about MIC experience and best practice recommendations using Intel Xeon Phi based systems like e.g. Salomon @ IT4Innovations (Czech Republic), the largest Intel Xeon Phi based system in Europe.

For details and registration see   https://www.lrz.de/services/compute/courses/2016-06-27_hphi1s16/ 

The workshop is collocated with a three-day scientific workshop on High Performance Computing for Water Related Hazards  taking place at LRZ on June 29 - July 1, 2016. See   https://www.lrz.de/services/compute/courses/2016-06-29_hwrh1s16/