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Intel MIC Programming Workshop

Date: 
Wed, 02/03/2016 - 9:30am to Thu, 02/04/2016 - 3:30pm
Registration deadline: 
Wed, 01/27/2016 - 11:30pm
Venue: 
VŠB - Technical University Ostrava, IT4Innovations building, room 207
Tutor: 
Volker Weinberg, Momme Allalen (Leibniz Supercomputing Centre), Branislav Jansík (IT4Innovations)
Level: 
Basic/Intermediate
Language: 
English

Annotation

The course discusses Intel’s new Many Integrated Core (MIC) architecture. It covers various programming and optimisation techniques for Intel  Xeon Phi coprocessors. The hands-on sessions are done on the new Intel Xeon Phi based Salomon system at the Czech National Supercomputing Centre IT4Innovations.

The course is developed within the joint German-Czech Republic project CzeBaCCA. A one-day workshop on Seismic Simulation Software of this project will take place at IT4Innovations directly after this course, on February 5, 2016 - see its web page for details.

About the tutors

Volker Weinberg studied physics at the Ludwig Maximilian University of Munich and later worked at the research centre DESY. He received his PhD from the Free University of Berlin for his studies in the field of lattice QCD. Since 2008 he is working in the HPC group at the Leibniz Supercomputing Centre and is responsible for HPC and PATC (PRACE Advanced Training Centre) courses at LRZ, new programming languages and the Intel Xeon Phi based system SuperMIC. Within PRACE-4IP he took over the leadership to create Best Practice Guides for new architectures and systems.

Momme Allalen received his Ph.D in theoretical Physics from the University of Osnabrück in 2006. He worked in the field of molecular magnetics through modelling techniques such as the exact numerical diagonalisation of the Heisenberg model. He joined the Leibniz Computing Centre (LRZ) in 2007 working in the High Performance Computing group. His tasks include user support, optimisation and parallelisation of scientific application codes, and benchmarking for characterising and evaluating the performance of high-end supercomputers. His research interests are various aspects of parallel computing and new programming languages and paradigms.

Branislav Jansik has obtained his PhD in computational chemistry at Royal Institute of Technology, Sweden in 2004. He took postdoctoral position at IPCF, Consiglio Niazionale delle Ricerche, Italy,  to carry on development and applications of high performance computational methods for molecular optical properties. Since 2006 he worked on development of highly parallel optimization methods in the domain of electronic structure theory at Aarhus University, Denmark. In 2012 he joined IT4Innovations, the Czech national supercomputing center as a head of supercomputing services. He published over 35 papers and co-authored the DALTON electronic structure theory code

Preliminary schedule

Wednesday  February 3,  2016
  
09:30-10:00

Registration

10:00-10:15

Welcome

10:15-11:30Salomon intro (Jansik)
11:30-13:00

Lunch break

13:00-14:30

Overview of the Intel MIC architecture and programming models, native mode programming (Allalen/Weinberg)

14:30-15:00

Coffee break

15:00-16:30OpenMP and offloading, Part 1 (Weinberg) 
16:30-17:00

Coffee break

17:00-18:00OpenMP and offloading, Part 2 (Weinberg) 

 

Thursday   February 4,  2016
  
09:00-10:30MPI (Weinberg) 
10:30-11:00

Coffee break

11:00-12:45MKL (Allalen) 
12:45-14:00

Lunch break

14:00-15:30

Vectorisation and basic Xeon Phi performance optimisation (Allalen/Weinberg)

 

Prerequisites

Good working knowledge of at least one of the standard HPC languages: C, C++ or Fortran. Basic OpenMP and MPI knowledge useful. Please bring your own laptop for the hands-on sessions.

Registration

Obligatory registration - registration form closed; deadline see above or exhausted course capacity.

Fees

The event is provided free of charge for the participants.

Capacity

30 attendees

Practicalities

Acknowledgements

 

Attachments: