Jste zde

Intel Xeon Phi programming (PTC course)

Čt, 01.03.2018 9:30 - Pá, 02.03.2018 16:30
Uzávěrka registrace: 
Po, 26.02.2018 23:00
VŠB - Technical University Ostrava, IT4Innovations building, room 207
Georg Zitzlsberger, Martin Golasowski, Michal Merta (IT4Innovations)


The course focuses on optimization oriented programming for the latest Intel Architectures for HPC. It covers state of the art Intel Architecture features, changes among the recent generations and trends to support HPC software developers and researchers in designing their applications. During the two day course also software development and analysis tools are covered as needed for C/C++ & Fortran development with the focus on performance, vectorization and energy efficiency. The course furthermore includes an overview of the latest OpenMP 4.5 standard including different ways of threading applications, how to leverage vectorization and offloading.

Purpose of the course (benefits for the attendees)

Participants will learn about the latest Intel Architectures, common problems and pitfalls dedicated to HPC, how to select and apply various software development tools, as well as the state of the art OpenMP programming techniques.

About the tutors

Georg Zitzlsberger formerly worked for Intel Deutschland GmbH (Germany). He has been a Technical Consulting Engineer for Intel(R) Software Development tools for many years before he recently joined IT4Innovations. In his new role as researcher he offers consulting services for Intel Software Development tools and Intel architectures throughout the IT4Innovations network.

Martin Golasowski is a research assistant and a Ph.D. student in the Advanced Data Analysis and Simulation Laboratory of the IT4Innovations National Supercomputing Center of the Czech Republic. Topic of his research are high performance programming models for Monte Carlo methods and emerging heterogenous architectures. He also contributes to a H2020 project ANTAREX as a developer of benchmarking infrastructure of an experimental server-side routing service. His other interests include parallel computing architectures, data processing and visualisation.

Michal Merta is a researcher at IT4Innovations National Supercomputing Center. He obtained his Ph.D. degree in Applied mathematics. He is mainly interested in the parallel boundary element method (BEM) and is a co-founder of the library BEM4I that aims at parallel solution of problems from linear elasticity to sound scattering using BEM. He participated within the Intel Parallel Computing Center (IPCC) project at IT4Innovations and has experience with code parallelization, vectorization and acceleration using the Intel® Xeon Phi™ coprocessors.

Preliminary agenda

Day 1
9:30 – 10:00


10:00 – 11:15

11:15 – 12:00

Latest Intel Architectures for HPC

Performance: How to achieve it?

12:00 – 13:00


13:00 – 13:45

13:45 – 14:30

Intel Compilers for C/C++ and Fortran

Profiling: Understand your application

14:30 – 15:00

coffee break

15:00 – 16:30

Hands On: Profiling



Day 2
9:00 – 10:30    OpenMP 4.5: Threading, offloading & vectorization 
10:30 – 11:00

coffee break

11:00 – 12:00Vectorization quality & metrics
12:00 – 13:00lunch
13:00 – 14:30

Hands On: OpenMP 4.5 (threading, offloading & vectorization)

14:30 – 15:00coffee break

15:00 – 16:00

16:00 – 16:30

Energy measurement on Intel Architectures



Advanced knowledge of C/C++ and/or Fortran is mandatory. Knowledge of OpenMP fundamentals is helpful.


Obligatory registration via the PRACE Events Portal.

Capacity and Fees

30 participants. The event is provided free of charge.


  • See the links below for how to get to the campus of  VŠB - Technical University Ostrava, and to the IT4Innovations building.
  • Documentation for IT4Innovations' computer systems is available at https://docs.it4i.cz/.


This training is a PRACE Training Centre (PTC) course, co-funded by the Partnership of Advanced Computing in Europe (PRACE). The main web page of the course is located on the PRACE Events Portal.