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Intel® Xeon Phi™ Co-Processor Workshop

Čt, 15.05.2014 9:00 - Pá, 16.05.2014 15:15
VŠB - Technical University Ostrava, FEI building, room EC3
Georg Zitzlsberger, Michael Steyer (Intel Germany)
intermediate / advanced


The availability of Intel Xeon Phi Coprocessor opens opportunities in the HPC domain for highly parallel algorithms/applications by providing a large amount of processing cores, each with 512 bit large SIMD vectors. While the programming models of the coprocessor are not much different to the ones known from Intel Xeon systems, there are still some specific characteristics.

The workshop will provide an overview about the most important aspects when writing new applications for the coprocessor or porting existing ones. A large portion of the workshop will be spent on how to optimize for the coprocessor. Participants will learn, that this is less specific to the coprocessor as anticipated and that key aspects learned can also be applied to tuning Intel Xeon based applications.

The workshop is split into two days. The first day contains lectures (with live demonstrations where applicable), providing a broad but compact overview about the coprocessor ecosystem. The second day allows participants to apply the learned aspects with lab exercises using Intel Xeon Phi Coprocessors.

Purpose of the course (benefits for the attendees)

The first day of the workshop contains an introduction to software development for the Intel Xeon Phi Coprocessor. Participants learn about the architecture, software infrastructure, supported programming models, MPI programming and analysis. The focus will be on optimizations and performance considerations.

The second day builds on information learned during the first day and provides advanced coverage with hands-on lab exercises. Participants work on predefined exercises that address a wide range of aspects, getting familiar with the Intel Xeon Phi Coprocessor infrastructure and programming. It also highlights optimization and MPI specific key concepts. Finally, the day concludes with an advanced performance analysis using VTune Amplifier XE.

After the workshop, participants will be able to start porting and tuning their own applications for the Xeon Phi Coprocessor. Lectures and lab exercises address both C/C++ and Fortran.

Schedule outline

Thursday, May 15, 2014:
09:00-9:45registration, workshop opening
09:45-12:30Workshop (block 1)
11:30-12:00time for lunch
13:30-17:45Workshop (block 2)
17:45workshop day 1 closing
Friday, May 16, 2014:
08:00workshop day 2 opening
08:00-12:30Workshop (block 3)
time for lunch
13:30-15:15Workshop (block 4)
15:15workshop closing

Detailed agenda


First day:   None
Second day:   Participants should bring their own laptops, with WiFi. A SSH & VNC client is required and should be installed prior the event (e.g. Putty & RealVNC). Some lab exercises might require a PDF viewer and/or web browser.


Obligatory registration - registration form here; deadline May 8, 2014 or exhausted course capacity.


50/30 attendees