Jste zde

Developing efficient HPC applications for the latest CPU architectures with C++ and Fortran (PTC course)

Po, 14.01.2019 9:30 - Út, 15.01.2019 17:00
Uzávěrka registrace: 
Po, 07.01.2019 23:00
VŠB - Technical University Ostrava, IT4Innovations building, room 207
Georg Zitzlsberger, Jakub Beránek, Radim Vavřík (IT4Innovations)


The course is two-fold: It provides an update on the latest state of the art CPU architectures for HPC and connects them to modern programming in C++ and Fortran.

Covered are all major CPU architectures common in HPC such as Intel (Xeon Scalable Processors), AMD (Epyc) and PowerPC (Power 9). These architectures will be explained in terms of needs for software developers and researchers to utilize their full potential, such as SIMD extensions, cache hierarchies, NUMA configurations, multi-core/-threading, memory bandwidth, throughput, etc.

For each of the addressed architectural properties, techniques and software design patterns are discussed that can be leveraged in modern high-level languages C++ and Fortran. Aside from standardized high-level language features, also compiler specific extensions are highlighted for the latest compilers like GCC/GFortran, LLVM Clang/Flang, IBM XL C++ & Fortran compilers, and Intel C++ & Fortran compilers.

The course will contain up to 50% hands-on exercises covering all topics to practice the techniques and patterns gained.

About the tutors

Georg Zitzlsberger formerly worked for Intel Deutschland GmbH (Germany). He has been a Technical Consulting Engineer for Intel(R) Software Development tools for many years before he recently joined IT4Innovations. In his new role as researcher he offers consulting services for Intel Software Development tools and Intel architectures throughout the IT4Innovations network.

Jakub Beránek obtained his Master's Degree in Computer Science and Technology at VŠB - Technical University of Ostrava in 2018. In the same year he joined IT4Innovations as a research assistant at the Advanced Data Analysis and Simulations Laboratory, where he is working on distributed programming models.

Radim Vavřík is a Ph.D. student in Computational Sciences and researcher in the Infrastructure Research Lab at IT4Innovations. He is mainly interested in parallel computing, scalable algorithms design, GPU acceleration and code optimization, and heterogeneous architectures. He worked on hydrological and flood modeling software, and high-performance heterogeneous platform for energy efficient computing. Now he is focused on GPU acceleration of the ESPRESO library, a massively parallel library based on the finite element method (FEM) for engineering applications.

Preliminary agenda

Day 1
9:30 – 10:00


10:00 – 12:00

Architecture comparison: Intel Xeon Scalable Processor, AMD Epyc & IBM Power9

13:00 – 14:30

C++ and Fortran Compilers for Intel & AMD architectures incl. Hands-On

15:00 – 16:30C++ and Fortran Compilers for IBM architectures incl. Hands-On
16:30 – 17:00Q&A


Day 2
9:00 – 10:30C++ and Fortran design patterns for Intel architectures incl. Hands-On
11:00 – 12:30

C++ and Fortran design patterns for AMD architectures incl. Hands-On


13:30 – 15:00

C++ and Fortran design patterns for IBM architectures incl. Hands-On 

15:00 – 15:30



Basic knowledge of HPC technologies (i.e. MPI, OpenMP); intermediate knowledge of Linux, and C++ and/or Fortran.


Obligatory registration via the PRACE Events Portal  and its registration form.

Capacity and Fees

30 participants. The event is provided free of charge.


  • See the links below for how to get to the campus of VŠB - Technical University Ostrava, and to the IT4Innovations building.
  • Documentation for IT4Innovations' computer systems is available at https://docs.it4i.cz/.


This training is a PRACE Training Centre (PTC) course, co-funded by the Partnership of Advanced Computing in Europe (PRACE). The main web page of the course is located on the PRACE Events Portal.


This course was supported by the PRACE-5IP project – the European Union's Horizon 2020 research and innovation programme under grant
agreement No. 730913.